IWLPC (Wafer-Level Packaging) Conference Proceedings


Deposition Processes for Competitive Through Silicon Via Interposer for 3D

Authors: Cyprian Uzoh, Rezwana Sharna, Pejman Monajemi, Michael Newman, Charles Woychik and Terrence Caskey
Company: Invensas Corporation
Date Published: 11/5/2012   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The 3D-IC and related technologies enables higher device and package bandwidth, improved device performance at lower power consumption, reduced form factor, and the potential for lower cost for applications in logic and memory integration including heterogeneous technologies in a single package. Invensas Corporation is pursuing many unique enabling solutions to address many of the most difficult 3D-IC fabrication challenges. The convention methods for the design and implementation of Through Silicon Via (TSV) interposer is reviewed. These various process modules include TSV etch, TSV fill, chemical mechanical polishing (CMP), BEOL, Bonding backside silicon removal processes, via reveal, passivation, wiring and bumping. These technologies were developed using 200mm and 300mm foundry equipments ranging from chemical vapor deposition (CVD), physical vapor deposition (PVD), deep reactive ion etching (DRIE), electrochemical deposition (ECD), silicon grinding, CMP, temporary bonding and de-bonding and various cleaning steps. Efforts on optimizing some of the most expensive processing steps, especially the metal filling in deep multimicron via cavities is discussed. The difficulties of depositing void-free deep via cavities and the differences between conventional BEOL and newer TSV plating chemistries, cost reduction methodologies will be presented.

Key Words: 

tsv, drie, ecd, beol, bottom up, cavity fill efficiency, plating planarization factor, gapfill anisotropic index, additives



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