IWLPC (Wafer-Level Packaging) Conference Proceedings


Evaluating Methods of Shipping Thin Silicon Wafers for 3D Stacked Applications

Authors: Richard A. Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David Read, Andreas Fehkührer and Jürgen Burggraf
Company: SEMATECH, NIST, Qualcomm, and EV Group
Date Published: 11/5/2012   Conference: IWLPC (Wafer-Level Packaging)


Abstract: An experiment was performed to develop a method for choosing appropriate packaging for shipping 300 mm silicon wafers thinned to 100 µm or less for threedimensional stacked integrated circuits (3DS-ICs). 3DSICs hold the promise of improved performance and/or lower power consumption for a given function by combining multiple chips into a 3D structure. However wafers thinned to 100 µm or less, which may be sourced from fabrication facilities anywhere in the world, must be collected in a single location for integration into 3D stacks. The methods evaluated were based on the procedure specified in ISO 2248:1985, entitled “Packaging – Complete, filled transport packages – Vertical impact test by dropping.” Four types of wafer packaging systems were tested. Wafers 50 µm and 100 µm thick and drop heights of 800 mm and 1200 mm were selected. A few wafers fractured during some of the tests, mainly those wafers with significant edge defects.

Key Words: 

Drop tests, finite element modeling, temporary wafer bonding, three-dimensional stacked integrated circuits (3DS-IC), wafer bonding, wafer shipping.



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