IWLPC (Wafer-Level Packaging) Conference Proceedings

Wafer-Level Testing Challenge For Flip Chip and Wafer-Level Packages

Authors: Lim Kok Hwa and Andy Chee
Company: STATS ChipPAC Ltd.
Date Published: 11/5/2012   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Wafer-level packages continue to see strong growth driven by mobile phones, portable players, digital cameras and tablets. All these devices use small form factor and low profile packages such as a wafer-level chip scale package (WLCSP) as it fits the requirements. Conventional flip chip die with solder bump is growing due to the increasing number of new design packages converting from wire bond and new flip chip interconnects such as copper pillar and micro bump are growing as a result of strong demand in 3D stacked ICs. Both WLCSP and flip chip need to be electrically tested in wafer format at some point in the assembly process, either as a Known Good Die (KGD) in 3D ICs or an end product that goes into the PCB of an electronic gadget.

Wafer sort or wafer-level testing was once considered as a method to save packaging cost as this process sorts out bad die before it is assembled into a package. However, today wafer sort or wafer-level testing is an important process for yield enhancement of flip chip packages and a final test requirement for WLCSPs.

The challenge of wafer-level testing has grown significantly due to the increasing complexity of the die or packages. The current technology started to see limitations in hardware and tools. This paper investigates the challenges facing waferlevel testing as well as examining the solutions available to overcome these challenges, identifying the gaps and additional innovation needed to overcome these challenges.

Key Words: 

Wafer-level, flip chip, testing

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