Wafer-Level Testing Challenge For Flip Chip and Wafer-Level PackagesAuthors: Lim Kok Hwa and Andy Chee
Company: STATS ChipPAC Ltd.
Date Published: 11/5/2012 Conference: IWLPC (Wafer-Level Packaging)
Wafer sort or wafer-level testing was once considered as a method to save packaging cost as this process sorts out bad die before it is assembled into a package. However, today wafer sort or wafer-level testing is an important process for yield enhancement of flip chip packages and a final test requirement for WLCSPs.
The challenge of wafer-level testing has grown significantly due to the increasing complexity of the die or packages. The current technology started to see limitations in hardware and tools. This paper investigates the challenges facing waferlevel testing as well as examining the solutions available to overcome these challenges, identifying the gaps and additional innovation needed to overcome these challenges.
Wafer-level, flip chip, testing
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