Board Level Reliability And Assembly Process Of Advanced QFN Packages
Authors: Li Li, Brian Smith, Joe Smetana, David Geiger, Chris Katzko, Jeffrey ChangBing Lee, Richard Coyle, and Alex Chan Company: Cisco Systems, Inc., HDP User Group International, Inc., Alcatel-Lucent, Flextronics, TTM Technologies, and IST-Integrated Service Technology, Inc. Date Published: 10/14/2012
Abstract: The quad flat no-lead (QFN) package has been used widely since its introduction in 1998. In the past few years, advanced QFN packages with large body sizes (>10 mm) and multi-row external terminals (two or more rows) as well as small body devices with ultra-fine pitch (<0.35 mm) pads have emerged as a cost & performance competitive alternative to other BGA styles packages, particularly for small form factor products. This paper presents a comprehensive study, conducted by the High Density Package (HDP) User Group, evaluating both board level reliability and assembly process yields for selected advanced QFN packages. The project was supported by a range of QFN package suppliers, contract assemblers, and system OEMs. Over 20 QFN components with a broad spectrum of package body and die sizes, varying numbers of termination rows, lead-frame surface finishes and terminal pitches were selected for the investigation. Several thousand fine pitch devices were mounted to identify optimum printed circuit board (PCB) design and process parameters. Temperature cycling tests (0 to 100°C) with two different dwell times at 10 minutes and 60 minutes were used for the board level reliability analysis. The experimental results were used to develop best practice design and assembly recommendations.