SMTA International Conference Proceedings


Material And Process Optimization For HiP Defect Elimination

Authors: Timothy Jensen, Ronald Lasky, Ph.D., PE, and Sehar Samiappan
Company: Indium Corporation
Date Published: 10/14/2012   Conference: SMTA International


Abstract: The area array package is an important component in modern electronics products. From mobile phones, tablets, and PCs to aerospace, area array packages are essential to the functioning of electronics. Prismark estimates that in 2013, over 30 billion area array packages, such as chip scale (CSP) and ball grid array (BGA) will be assembled. This works out to be more than four packages for every man, women, and child on the earth. However, in recent years, a new area array assembly defect mode called head-in-pillow (HIP) has been identified. HIP is a defect associated primarily with BGAs due to their internal CTE mismatches and tendency to warp. HIP is so named because a cross-section of the HIP defect within a BGA solder joint looks like a head in a pillow.

Key Words: 

Head-in-Pillow, process optimization



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