SMTA International Conference Proceedings


3D Packaging For High Computing With Wide IO Processor-Memory Interface

Authors: Ilyas Mohammed, Ron Zhang and Rajesh Katkar
Company: Invensas, Inc.
Date Published: 10/14/2012   Conference: SMTA International


Abstract: High computing is trending towards multi-core, low power processors at both client and cloud nodes. This has placed a high premium for high processor-memory bandwidth through a very large number of IO with short physical length. This is best achieved by stacking memory on top of the processor. This offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVATM) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, cleaning the wire tips, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.

Key Words: 

Bond Via Array, processor-memory interconnect, wide IO memory, high computing package



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