Investigations Into 0.3mm Pitch Assembly and Reliability
Authors: Denis Barbini, Ph.D., and Michael Meilunas Company: Universal Instruments Corporation Advanced Process Laboratory Date Published: 10/14/2012
Abstract: 0.3mm pitch Wafer Level and Chip Scale Package assemblies utilizing printing and dipping processes were evaluated for high-yield, high-throughput lead-free applications. Multiple stencil thickness, aperture sizes, paste/flux types, printer and placement machine settings were evaluated and the optimum, or near optimum, parameters were used to assemble components to multi-layer test boards. Package designs evaluated included a 256 I/O standard array CSP, a 400+ I/O staggered array CSP and a 100 I/O WLCSP. Motherboards with open and copper filled microvia-in-pad were included in the comparisons. The completed test vehicles were subjected to mechanical shock (i.e. drop) testing, cyclic four-point bending, and/or thermal cycling in order to perform comparative reliability analyses.