Development and Optimization of Through Silicon Via Interposers
Authors: Pejman Monajemi, Michael Newman, Cyprian Uzoh, Charles Woychik, Lina Ayat, and Terrence Caskey Company: Invensas Corporation Date Published: 10/14/2012
Abstract: Through Silicon Via (TSV) interposer shows high sensitivity to design and process variations. This paper provides a summary of interposer design and fabrication optimization, effect of different process modules on the interposer performance with the emphasis on the frontend process. Two different cylindrical copper TSV’s of 20µm and 10µm diameter and 100µm depth are fabricated in silicon. The frontend process includes Redistribution Layer (RDL), TSV etch and fill, Chemical Mechanical Polish (CMP), and pad finish on solder pads. The backend includes temporary bonding, thinning, via reveal, passivation, wiring, bumping and de-bonding. Efforts on optimizing the profile and sidewall roughness through Deep Reactive Ion Etch (DRIE) and cleaning are discussed. Step coverage of Tantalum and silicon nitride barrier layers, deposited by Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD) is discussed. TSV profile after copper via fill by Electrochemical Deposition (ECD) is reported. Thermal slide and room temperature slide processes for temporary bonding and de-bonding were evaluated. Finally, a summary of TSV fabrication issues, solutions, and microbump assembly is presented.