Drop Reliability Test On Different Dimensional Lead-Free Wafer Level Chip Scale Packages
Authors: Sivasubramanian Thirugnanasambandam, Namo Vijayakumar, Jiawei Zhang, John Evans, Ph.D., Fei Xie, Ph.D., and Daniel F. Baldwin, Ph.D. Company: Auburn University and Engent, Inc. Date Published: 10/14/2012
Abstract: In this experiment, a solder ball grid array interconnect has been studied for reliability. The drop performance of different dimensional lead free wafer level chip scale package on laminate assemblies with SAC 305 alloys (3% Ag, 0.5%Cu) were recorded, to determine their reliability based on optimal dimensions of ball grid array and polymer coat package structures. The test chips were of 6 X 6, 8 X 8 and 12 X 12 ball grid array packages with perimeter solder balls on a 0.4 mm pitch. The WLCSP assembly was subjected to high impact accelerated life test of 400 drops per board with 1500G, 0.5 millisecond half sine pulse. The test boards were built to withstand JEDEC JESD22-B111 standards of high stress test in drop towers to assess the solder joint performance. Reliability of the test chips were determined from the ability of the solder interconnects to withstand the mechanical stresses induced by the drops. The SAC alloy micro structures of the components were studied in a scanning electron microscope to determine the impact of the intermetallic components on the solder joint reliability. The results showed that the main crack initiation position was at the top side of the solder joints (near the chip side). The results showed that the 6 X 6 ball grid array packages had better reliability and on the 12 X 12 packages the CSPn3 had better reliability than the CSPn2.
WLCSP, BGA, PCB, Reliability, SEM, Solder, SAC 305, lead free, Flip Chip, HALT, JEDEC