Copper Pillar Bump Process Characterization on 300mm Wafers
Authors: Wei Koh, Ph.D. Company: Pacrim Technology Date Published: 2/14/2012
Pan Pacific Symposium
Abstract: Copper Pillar Bump (CPB) technology is being adopted in many packages in mobile device due to its ability to accommodate very fine pitch flip chip interconnection and reduced package size. Increasingly, for 2.5D interposer and 3D IC integration packages, CPB is also being applied for die stacking and chip- to-interposer interconnect. The bump structure described here follows the metal post solder chip connect (MPS-C2) design. Key processes for fabricating fine-pitch CPB on large, 300mm wafer are described. Focus of the discussions is placed on the processing steps in photoresist coating, patterning, and the electrochemical deposition (ECD) control parameters such as the plating bath temperature and the plating current density. The resulting characteristic properties of the copper pillar bumps that varied with the changes in the processing parameters and conditions are compared. Based on these analyses, some guidelines for making high quality, and high yield copper pillar bumps on 300 mm wafers are given at the conclusion.