Pan Pacific Symposium Conference Proceedings


Silicon Interposer For A 12X10 Gb/s Electro-Optical Engine

Authors: Terry Bowen and Richard Miller
Company: TE Connectivity
Date Published: 2/14/2012   Conference: Pan Pacific Symposium


Abstract: The increasing transmission speeds in network switching, data storage, and super computing equipment makes it more and more difficult to use traditional electrical interconnects. Fiber optic links are a natural solution to this problem. Moving the optical fiber inside the box will demand smaller physical size modules that accommodate the increased density of high speed interconnects. This paper will present the design of small parallel optical transmitter and receiver assemblies that are surface mountable. They operate at 10 Gb/s today and are expected to migrate to 25 Gb/s in the near future.

The silicon interposer for this design provides top side electrical interconnects with flip chip mounting for a 1X12 Vertical Cavity Surface Emitting Laser (VCSEL) array die and a 1X12 VCSEL driver array die. A similar interposer is provisioned for a 1X12 photodetector array die and a 1X12 receiver array die. The solder pads on the VCSEL and photodetector arrays are precisely located relative to the optical apertures on each die. The silicon interposer has a matched set of solder pads that are precisely located relative to the end facets of the grooves that position the optical fibers in the final assembly.

When a wafer-scale solder reflow process is performed, surface tension of the molten solder pulls the corresponding pad arrays into precise alignment. The optical signals can be deflected 90 degrees into or out of the fibers by either cleaving the ends of the fibers at a 45 degree angle or by incorporating a 45 degree mirror at the end of the fiber grooves. This design eliminates the need for any additional optical coupling elements, and results in an arrangement, which has a very compact structure.

The input and output electrical traces for the ICs are routed on the top surface of the silicon interposer and are transferred to the back surface using through wafer vias. The populated interposer is diced from the wafer, and soldered to a printed circuit board or a high speed flex circuit.

Key Words: 

FLIP-Chip Passive Alignment, Silicon Interposer, Wafer-Scale Processing, Vertical Cavity Surface Emitting Laser Array (VCSEL Array), VCSEL Driver Array IC, Interconnect Bandwidth Density, Laser Fiber Endface Cutting, Through Wafer Vias, Chip-to-World Interconnects



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