Pan Pacific Symposium Conference Proceedings

3D Contactless Capacitive Coupled Interconnection Circuit Design

Authors: Yu-Jung Huang, Ph.D., Shen-Li Fu, Ph.D., Yi-Lung Lin, and Ming-Kun Chen, Ph.D.
Company: I-Shou University and Advanced Semiconductor Engineering Test RD
Date Published: 2/14/2012   Conference: Pan Pacific Symposium

Abstract: This paper describes a chip-to-chip circuit design suitable for three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) stacked applications. The proximity data link is performed via capacitive couplings between the top facing dies for three-dimensional system integration. The parasitic capacitances of coupling pads are one of the key parameters for the simulation of the signal integrity. The circuit has been simulated using TSMC 0.18 µm library and layout is developed by applying Laker Layout Software. The simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. This scalable capacitance characteristic enables the prediction and optimization of data-link-coupling performance.

Key Words: 

capacitive coupled interconnection; 3D

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