Authors: Risto Tuominen, M.Sc., Tuomas Waris, Tanja Karila, Janne Mettovaara, Markus Eklund, Sara Hardy-Baloun Company: Imbera Electronics Date Published: 10/3/2011
IWLPC (Wafer-Level Packaging)
Abstract: The rapid evolution of System-in-Package (SiP) modules has largely been driven by product miniaturization and performance. A major advantage of SiP over System-on- Chip (SoC) is improved time-to-market. It is possible to accommodate existing various technologies (surface mount, wire-bonding, flip-chip, component embedding) and component types (Si, GaAs, MEMS, discrete passives) in a single package which includes an entire system’s functionality. In hand-held applications surface space is at such a premium that many types of 3D stacking techniques have been developed to make use of zdimension. Embedding technologies are fundamentally ideal for 3D SiP structures, since some of the functions are embedded in the substrate; while the top layer is available for components assembled using traditional interconnection methods. Embedded substrates with vertical interconnections from the substrate top layer to package I/O lands provide a solution for effective utilization of the total package volume. This paper presents the next level of SiP volume utilization by illustrating 3D IMB® substrate structures. Significant form factor reductions are achieved by stacking embedded thin components. Case study cost comparisons with other SiP technologies are also presented.