IWLPC (Wafer-Level Packaging) Conference Proceedings


Cost Comparison Of Fine Pitch Chip Scale Packaging Technologies

Authors: Alan Palesko and Chet Palesko
Company: SavanSys Solutions LLC
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Miniaturization requirements continue to drive IC packages to be smaller and cheaper. A large number of chip scale packaging (CSP) suppliers and approaches are available to the designer, but these technologies fall into one of the following three technologies. ? Wafer Level Packaging – The package is fabricated on the wafer. A silicon wafer is used for fan-in WLP and a re-constituted wafer is used for fan-out WLP. ? Embedded Die – The die is placed on a partially completed substrate and the remaining substrate is fabricated around the die. ? Traditional fcCSP Packaging – The substrate is completed before the die is placed. All three of these technologies have advantages and disadvantages for different applications. In this paper, we will analyze these differences and key cost drivers for each technology using activity based cost modeling. Total cost results will be presented for a range of package sizes for each technology.

Key Words: 

cost modeling, CSP, fcCSP, Fan Out WLP, Embedded Die



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