IWLPC (Wafer-Level Packaging) Conference Proceedings


Wafer-Level Packaged MEMS Switch With TSV

Authors: Nicolas Lietaer, Thor Bakke, Anand Summanwar, Per Dalsjø, Jakob Gakkestad, and Frank Niklaus
Company: SINTEF, Department of Microsystems and Nanotechnology, Norwegian Defence Research Establishment (FFI), and Microsystem Technology Lab, School for Electrical Engineering, KTH – Royal Institute of Technology
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)


Abstract: A miniaturized wafer-level packaged MEMS acceleration switch with through silicon vias (TSVs) was fabricated, based on technologies suitable for harsh environment applications. The high aspect ratio TSVs were fabricated through the silicon-on-insulator (SOI) substrate prior to the fabrication of the MEMS structures. Doped polysilicon was used as the conductor for the TSVs, which has the advantage of a thermal coefficient of expansion that matches that of the silicon substrate material. The fragile MEMS structures were protected from the environment by wafer-level bonding of a glass cap using benzocyclobutene (BCB). The BCB layer which was spray-coated onto the patterned glass wafer provides a good bond strength and temperature stability. As opposed to having lateral interconnects at the interface between the cap wafer and the device wafer, the use of TSVs significantly reduces the footprint and allows flipchip bonding of the devices onto a substrate. The bare MEMS chips were mounted directly onto a printed circuit board (PCB) thereby avoiding an entire packaging level and reducing the system complexity and cost. This was done using an isotropic conductive adhesive (ICA) based on metalized polymer spheres, which is believed to be an interconnect technology more suitable for harsh environments than metal-based BGA and CSP technology. The initial characterization of completed chips mounted on a PCB shows promising results.

Key Words: 

through silicon via, TSV, MEMS switch, wafer-level packaging, ICA



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