IWLPC (Wafer-Level Packaging) Conference Proceedings

Evolution, Challenge, And Outlook Of TSV, 3D IC Integration And 3D Silicon Integration

Author: John H. Lau
Company: Electronics & Optoelectronics Research Laboratory, Industrial Technology Research Institute (ITRI)
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)

Abstract: 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, lowcost, and thermal-enhanced 3D IC integration system-inpackages (SiPs) with various passive TSV interposers are proposed.

Key Words: 

TSV, 3D IC integration, 3D Si integration, active and passive interposers, C2W and W2W bonding

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