IWLPC (Wafer-Level Packaging) Conference Proceedings

Identifying The Mechanism Of Stress-Assisted Void Growth In Through Silicon Via (TSV) By X-Ray Microscopy And Finite Element Modeling

Authors: LayWai Kong, James R. Lloyd, Ph.D., Michael Liehr, Ph.D., Alain C. Diebold, Ph.D., Ehrenfried Zschech, Ph.D., and Andrew C. Rudack
Company: College of Nanoscale Science and Engineering, SUNY Albany, Fraunhofer Institute (IZFP), and SEMATECH
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Void growth in through silicon vias (TSVs) has been imaged by X-ray microscope without physical cross sectioning. In additional, a finite element stress modeling is used to study the stress-assisted void growth. Fabrication of through silicon vias (TSVs) is challenging and often hampered by the presence of seam-line or voids inside the TSVs as pre-existing void. Annealing these TSVs induces large hydrostatic stress gradient distribute around the preexisting void. This hydrostatic stress gradient is the driving forces for the vacancies to diffuse to the pre-existing void region and causing void growth. Because physical cross sectioning of TSVs is not required for the 8KeV lab-based X-ray microscope, the same TSVs can be imaged before and after annealing. Void growth is observed at the pre-existing void location after annealing in TSVs with 5µm in diameter and 26 µm of depth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods and will be presented. The maximum of hydrostatic stress gradient is found to be around the void when cool down from annealing temperature to room temperature. The comparison between simulated results and experimental data show that void growth in TSV is stress-assisted, where vacancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient.

Key Words: 

Void growth, TSVs, hydrostatic stress gradient, 8keV, lab-based X-ray microscope.

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