IWLPC (Wafer-Level Packaging) Conference Proceedings


Development Of Next Generation eWLB (Embedded Wafer Level BGA) Technology

Authors: Yonggang Jin, Jerome Teysseyrex, Xavier Baraton, Seung Wook Yoon, Yaojian Lin, and Pandi Chelvam Marimuthu
Company: ST Microelectronics and STATS ChipPAC LTD
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. eWLB is one of key advanced packages because of advantages of higher number of I/Os, process easiness and integration flexibilities. Furthermore, it enables to integrate multiple dies vertically and horizontally in one package without using substrates. Thus, recently eWLB technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. This paper reports developments of next generation eWLB for advanced packaging solutions. A whole portfolio of next generation package configurations: 3D SiP/PoP, small outline eWLB and eWLL (embedded Wafer Level Land Grid Array) are developed. And the component and board level reliability study was carried out in depth by experimental approaches as well as failure analysis. Successful reliability characterization results on different package configurations are reported that demonstrate next generation eWLB as an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions.



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