IWLPC (Wafer-Level Packaging) Conference Proceedings

System-In-Package Opportunities With The Redistributed Chip Package (RCP)

Authors: Scott Hayes, Navjot Chhabra, Trung Duong, Zhiwei (Tony) Gong, Doug Mitchell, and Jason Wright
Company: Freescale Semiconductor
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Early development efforts on fan-out wafer level packaging (FO-WLP) focused on single die packages with single-sided redistribution. The key advantages of the initial FO-WLPs included package size reduction over other BGA packages as well as lower cost with higher IO opportunities than standard wafer level packaging without having to increase the die size to meet pitch and IO requirements. Another notable advantage of FO-WLP is the low-impedance, lowstress nature of the package interconnect with the die. Both of the aforementioned characteristics are made possible by the direct connection of the FO-WLP build up metallization to the die pad without the use of wirebonds or C4 solder. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPD’s gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology.

Key Words: 

Fan-Out Wafer Level Package (FO-WLP), System-in-Package (SiP), heterogeneous integration, 3D package integration

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