IWLPC (Wafer-Level Packaging) Conference Proceedings


Potential Of Large Area Mold Embedded Packages With PCB Based Redistribution

Authors: T. Braun, K.-F. Becker, L. Böttcher, A. Ostmann, E. Jung, S. Voges, T. Thomas, R. Kahle, V. Bader, J. Bauer, R. Aschenbrenner, M. Schneider-Ramelow, and K.-D. Lang
Company: Fraunhofer Institute for Reliability and Microintegration, and Technical University Berlin, Microperipheric Center
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the potential of advanced large area encapsulation processes for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing. PCB based redistribution offers the potential of real large area redistribution up to 610 x 457 mm² and the integration of through mold vias (TMVs) as both are standard features in PCB manufacturing. For the proposed combination of mold embedding and PCB based redistribution two process variations are introduced. The first approach starts with reconfigured wafer/panel assembly, encapsulation and PCB based redistribution with µvias for die interconnection. For the second approach dies are assembled face down on a Cu foil with an adhesive followed by an overmolding/ lamination step. The die interconnect is formed by a photolithography/etching step to open the Cu film at the locations of the die pads and the pads are connected by metallization afterwards. Process steps as assembly, encapsulation and redistribution on panel size are discussed in detail showing today’s possibilities. Finally, packages developed are introduced demonstrating the feasibility of the proposed technology. In summary this paper describes the potential of large area mold embedding technology in combination with PCB based redistribution processes towards a 3D SiP stack. The technology described offers a cost effective packaging solution for e.g. future sensor/ASIC systems or processor/memory stacks providing miniaturization and sourcing advantages known from PoP assembly.



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