IWLPC (Wafer-Level Packaging) Conference Proceedings

High Density TSV Chip Stacking Fabless Infrastructure Status

Author: Matt Nowak
Company: Qualcomm, Inc
Date Published: 10/3/2011   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The development of high density 2.5D and 3D TSV chip stacking technology is rapidly moving forward, with the establishment of prototype fabrication lines, assembly and test of demonstrator test vehicles, and characterization and engineering reliability data now available. Several chip stacking partitions are reportedly in development for productization, examples of which are shown in Figure 1. Development of JEDEC-standard wide IO DRAM is also proceeding, which will enable high bandwidth at low power. Wide IO DRAM can be stacked as a single die or as Micro Pillar Grid Array (MPGA) cubes either directly on logic die or side by side on a TSV interposer. Heterogeneous stacking of logic die on logic die fabricated in different technology nodes offers compelling opportunities for cost savings and design reuse. 2.5D TSV interposers are likely to be the first partition to be productized, since TSVs are only required in the inactive interposer and not in the chips with active circuits.

Considerable knowledge has been gained with respect to previously perceived challenges, including high aspect ratio (~10:1) via formation, backside wafer processing, microjoining, test/DFT, thermal/mechanical integrity, design methodologies, and intrinsic reliability. Integrated process modules for via-middle formation, including high aspect ratio silicon etch, liner and barrier/seed deposition, copper fill, and CMP overburden removal, and for tier to tier microjoining, are now established. Backside wafer processing, including temporary carrier mount and demount processes, have been successfully demonstrated and continue to be refined. Engineering reliability data collected from test vehicles has been used to identify reliability risks such as TSV copper pumping, driving process optimization to eliminate the failure modes and implementation of design rule constraints.

Thermal and mechanical integrity challenges associated with TSV chip stacking are highly dependent on the particular component and system-level design. Designfor- Thermal methodologies and the use of mechanical stress simulators are being developed to manage these interactions. ASIC Design and test/DFT methodology requirements are contingent on the specific system partition implemented. Designs with properly constrained partitions will require only limited extensions to existing 2D design methodologies and EDA tools.

Especially critical for the productization of high density TSV technology for high volume mobile wireless applications will be the readiness of the fabless supply chain infrastructure, including industry standards, supply chain business models for stacked memory cubes, and competitive pricing. Initial adoption of this disruptive new technology will depend on offering a compelling technical and business value proposition which cannot be attained by extending existing technical solutions.

Key Words: 

Chip stacking, high density, TSV, wafer

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