Defining Package Warpage Criteria To Mitigate Head And Pillow Defects
Authors: Paramjeet Singh Gill and Yoong Tatt Chin Company: Intel Corporation Date Published: 10/16/2011
Abstract: Electronics industry continues to drive miniaturization through smaller form factors enabled products with greater functionality. Thinner packages became very attractive as it enables lighter, slimmer and longer battery life devices. These thinner packages provide a reduction in overall package z-height from 1.07mm to 0.77mm thickness. Unfortunately, the introduction of thinner packages produces higher outgoing package coplanarity due to less stiff package which is the governing issue effecting assembly yields. As the current JEDEC standard was not designed for the demands of thin products, Intel has provided industry leadership in revising this standard to enable thin-core BGA manufacturing which allows significant cost reduction and higher assembly yields. This paper will discuss on the integrated approach taken and new methodology defined to enable this technology by demonstrating permissible surface mount (SMT) and rework capability which does not meet current outgoing package coplanarity sets by JEDEC standard. A “High-Temperature Compensation” approach enables suppliers such as Intel to demonstrate good surface mount (SMT) capability by characterizing a component’s dynamic warpage behavior throughout the full reflow temperature range during SMT. The new approach utilizes Shadow Moiré techniques coupled with statistics to provide the room temperature (RT) high-volume manufacturing (HVM) monitoring capability for Intel’s outgoing products.
Warpage, thin package, thin-core substrate, SMT, JEDEC, high temperature warpage.