Surface Mount International Conference Proceedings


REDUCTION OF PIN TEST FALSE FAILURES IN A NO-CLEAN PRODUCTION ENVIRONMENT

Author: Kuan-Shaur Lei
Company: Compaq Computer Corporation
Date Published: 4/28/1997   Conference: Surface Mount International


Abstract: A series of evaluations of the process-pin test relationship were performed. The objectives of these studies were to (1) quantitatively understand the effects of process and test parameters on test yield, and (2) identity the key factors in maintaining high pin test yields. The first step was to accurately monitor ICT failures, and the next phase was to determine the root causes for these failures. Many factors, both process variables and test parameters, were found to impact the in-circuit test (ICT) yield, Furthermore, operator experience, training, and discipline can increase or reduce the extent of test difficulties. After the important variables had been identified, several designs of experiments (DOES) were performed in order to determine the effectiveness of process and test variables on ICT yield. The process variables examined included solder paste, flux quantity, flux distribution, and wave solder parameter while the test parameters examined included vacuum pressure, pin stroke, board warp, and registration. The studies concluded that high ICT yield in a no-clean process environment can be achieved by precise control of process and test variables. As a result of this control, very low ICT false failures, high line through-put, and low test fixture maintenance can be attained. Keywords: In-circuit-test, No-clean, Pin test, Autoprobe



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