Author: Vern Solberg Company: STC-Madison Date Published: 10/16/2011
Abstract: The current market driver for semiconductor package technology is to provide more functionality and improve performance without increasing package size. Vertically configured 3D package technology addresses this issue for a broad number of enterprise products. Initially, the 3D package contained two or more semiconductor die elements mounted on top of one another, most often interconnected using a common substrate interposer. Adapting through silicon via (TSV) technology for die-on-die interface on the other hand has the potential to further improve both package performance and package assembly efficiency. Progress in this area has accelerated through the cooperation and joint development programs between a number of government, industry and technical universities. Although the TSV process is touted as the ‘next big thing’ in semiconductor packaging, capabilities and methodologies for providing wafers and die elements for stacking currently vary a great deal between suppliers. Although TSV technology has the potential to revolutionize semiconductor packaging, it currently remains hostage to a very limited homogeneous family of products; MEMS, memory and image sensors. In addition, there are a number of processes and methodologies that are considered proprietary and may require licensing agreements and additional fees for there use. Industry roadmaps, however, continue to point toward the eventual use of TSV in developing new generations of high performance system-in-package products. This paper will explore three basic approaches to TSV formation, via-first, via middle and via-last: Via-first integration forms very small via holes in the wafer prior to front-end processing. The via-middle formation follows front-end wafer level processes. Via-last integration will occur after bonding wafers or joining individual die elements to one another (Die-on-Die). Due to the increased thickness of pre-joined die, the via-last process typically provides somewhat larger via holes.
3D semiconductor packaging, through silicon via, TSV, die stack, wafer stack