Processing Strategies And Reliability Of 3D Wafer Level Csps
Authors: Fei Xie, Ph.D., Zhaozhi Li, Ph.D., Daniel F. Baldwin, Ph.D., Paul N. Houston, Brian J. Lewis Company: Auburn University, Engent, Inc. – Enabling Next Generation Technologies Date Published: 10/16/2011
Abstract: A 3D Wafer Level CSP packaging architecture that provides a cost effective, rapid time to market alternative to emerging 3D die to wafer integration technologies has been previously introduced. This paper continues beyond the first level work and focuses on the second level assembly process development and reliability performance assessment of the 3D WLCSP packages. The second level assembly, to date, shows robust yield and solid reliability performance through 1500 air-to-air thermal cycles on packages under various assembly process conditions. Manufacturing process challenges such as underfill encroachment, underfill voiding and Pb free CSP reflow profile parameters, as well as different underfill methodologies are discussed. The impact of select solder pastes on overall reliability will also be covered. An analysis of the yield on both fine pitch and coarser pitch WLCSP structures will be detailed, in addition to, reviewing different underfill processing schemes that were utilized to solve the underfill encroachment issue on fine pitch first level packages. Some of the material selections and their impact on yield and reliability will also be covered. Finally, the reliability assessment on the second level package assembly shows that the structured 3D-WLCSP packages can be fabricated with robust yields and demonstrate high reliability.
3D Wafer Level CSP (WLCSP), Assembly process, Second level, Yield, Reliability.