FAILURE OF THICK BOARD PLATED THROUGH VIAS WITH MULTIPLE ASSEMBLY CYCLES-- THE HIDDEN BGA RELIABILITY THREAT
Author: Kevin T. Knadle Company: IBM Microelectronics Date Published: 4/28/1997
Surface Mount International
Abstract: The combination of aggressive assembly processes and high aspect ratio non-solder filled wiring vias (PTVsi) on the host board, which increasingly characterize BGA technology in the 1990s, can lead to fractures in the vias during assembly that are not detectable with high efficiency by in-circuit tests. This reliability threat is demonstrated with thermal profiles from assembly and high temperature fatigue data using the Current Induced Thermal Cycles test, along with actual product examples of assembly induced fails. The effect of temperature, PTV defects, and surface finish (OSP, Ni/Au, HASL) on via reliability is shown.