Pan Pacific Symposium Conference Proceedings

Thin Wafer Processing And Chip Stacking For 3D Integration

Authors: Thorsten Matthias, Daniel Burgstaller, Markus Wimplinger, and Paul Lindner
Company: EV Group
Date Published: 1/18/2011   Conference: Pan Pacific Symposium

Abstract: Stacking of thin dies with Through-Silicon-Vias (TSV) is a very promising technology for “More than Moore” chip architectures. The vertical interconnects enable better electrical performance, smaller form factors, heterogeneous integration and modular chip architectures. Compared to classical chip manufacturing 3D integration requires the adoption of several disruptive manufacturing technologies e.g. deep via etching and filling, thin wafer processing and chip stacking with TSVs. All of these technologies have to be introduced in parallel into chip manufacturing. The individual unit processes are well qualified for applications in MEMS and Compound Semiconductors. The key challenge is the integration of all these unit processes for a complete TSV and 3D manufacturing line. In this paper the state-of-the-art of temporary bonding and debonding, chip-to-wafer bonding and wafer-to-wafer bonding is reviewed with an emphasis on the manufacturing integration. Key words: 3D integration, thin wafer handling, temporary bonding, wafer bonding, chip-to-wafer bonding

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