Pan Pacific Symposium Conference Proceedings

Geometric Downscaling – A Challenge For Process Chemicals And Materials

Authors: Sven Lamprecht, Hugh Roberts, and Chisato Okawa
Company: Atotech
Date Published: 1/18/2011   Conference: Pan Pacific Symposium

Abstract: For the electronics packaging industry, maintaining pace with the continuing reduction of integrated circuit (IC) node poses a major technological challenge. Specifically, following Moore's law (increasing the transistor count within the IC) also increases the complexity of manufacturing the package substrate that must support the IC. Other requirements impact the complete supply chain, such as product time-to-market, manufacturing yield and design cycles. The electronics evolution is combining requirements for performance, cost and form factor and is thereby posing serious challenges for the manufacture of the package substrate. New process technologies cannot be developed to address such requirements individually. The combination of all requirements must be considered, but with an individual assessment that depends on the specific function of the electronic product. To some extent, the transition from wire bond to flip chip packaging addresses both footprint and performance requirements, but further developments are occurring. IC packaging is already shifting from relatively simple array packages to more complex solutions including package-on-package (PoP), system-in-package (SIP) or other 3D approaches, such as die stacking. These shifts are enabling electronics designers and developers to serve as architects in achieving a functional level exceeding that established by Moore’s Law (“More than Moore”). Other supporting technologies, such as utilizing embedded active and passive components, will expand in their use in substrate fabrication to meet the demand for those future electronic products. This paper identifies limitations and opportunities that challenge the manufacture of advanced package substrates. However, the paper not only addresses the technical limitations of existing production processes, but also focuses on the “Three Evil M’s” that occur within the manufacturing process of a package substrate. Known in Japanese as Muda, Mura and Muri, the Three Evil M’s is a systematic approach for identifying, reducing and/or eliminating waste, which is a key component of “Kaizen”. Originating in Japan, Kaizen is a culture of sustained continuous improvement that seeks to minimize throughput time by eliminating non-value-added activities. This paper focuses not only on feature design and form factor, but also on the subject of sustainable manufacturing technologies and generation of “green electronic products”. Process chemicals and materials are offered as potential solutions to those individual challenges, where the right mix will enable a “More than Moore” culture, while continuing the battle with the “Three Evil M’s”. Key words: embedded conductors, through hole filling, BMV filling, non etching adhesion promotion (NEAP), RCF, RRCF

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