Pan Pacific Symposium Conference Proceedings

Device Level 3D Integration Technologies For High Performance/Reliability Modules

Authors: Paul Houston, Brian Lewis, Keck Pathammavong, Tim Sparks, and Daniel F. Baldwin, Ph.D.
Company: ENGENT, Inc.
Date Published: 1/18/2011   Conference: Pan Pacific Symposium

Abstract: As electronics continue towards higher performance and smaller form factors, interest in 3D die level integration has moved to the forefront. While current 3D packaging solutions, involving a combination of high density circuit boards with stacked ICs using wire bond interconnect, can satisfy some of the performance and form factor requirements, 3D die level integration is proving to be the solution of choice for many mission critical, applications. The key features of 3D die level integration are very high levels of integration, very small form factor packages (often chip scale in size), very low profile packages, low weight packages, and improved digital and RF performance. This paper will briefly review 3D integration technologies, present implementation strategies for 3D die level integration packaging, and present examples of 3D die level integrated packaging solutions.

Key words: 3D Integration, Flip Chip, Reliability, Die to Wafer Assembly, Die to Die Assembly, 3D Packaging

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