Pan Pacific Symposium Conference Proceedings

Economic Considerations In Choosing A TSV Deposition Technology

Author: Steve Lerner
Company: Alchimer, SA
Date Published: 1/18/2011   Conference: Pan Pacific Symposium

Abstract: Through Silicon Via (TSV) continues to unfold as the semiconductor industry’s paradigm of the decade. No other topic has gained such widespread conference coverage in recent years, yet the issue of cost remains largely blurred by blind faith in legacy tools and processes. Unfortunately, dry processes have failed to meet designers’ needs for narrow- diameter, deep vias, and have forced the industry down a path of short, wide vias dependent on carrier wafers, excessive fill times and costly equipment. However, as device-level performance pressure mounts and TSVs are employed as a device necessity, users are focusing on the actual costs associated with installation of these capital- intensive legacy lines, their design limitations, and the prospects of low yields. A realization that other options must be explored if chipmakers are to remain competitive is starting to sink in. This paper characterizes the economic benefits of a fully wet stack for 3-D TSV, starting with the inherent improvements in design rules, the scalability of process, and most important, the impact that a fully wet integrated process will have on capital equipment expenditures. By combining a unique set of materials and processes, a reliable and robust technology has been developed to dramatically enhance design rules, improve yields and reduce cost for the most aggressive TSV designs in the industry, 20:1 aspect ratios. It is now possible to sequentially deposit an isolation layer and a barrier layer and directly Cu-fill very deep and narrow diameter vias, all in one seamless low-cost tool, cassette in/cassette out. This paper will demonstrate the numerous points throughout the TSV fabrication process, before, during and after the deposition process, where dramatic cost savings can be achieved simply by processing to the structure, rather than compromising the structure for the tool. Typical illustrations will demonstrate how Si real-estate cost can be slashed by 300 USD per wafer and how capital expenditures can be cut by over 60%, all while improving device performance. Finally, reliability data will also be presented, providing an equally compelling argument for wet vs. dry TSV films.

Key words: TSV, 3-D, Interposers, Wet Thin Film Deposition, Wafer-Level Integration.

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