IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Jeff S. Leal, Suzette K. Pangrle, Charles Whyte, Keith Barrie, Jeff Leff, Scott McGrath and Gerardo Ayala
Company: Vertical Circuits, Inc
Date Published: 10/11/2010   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The use of dispensable conductive materials to create fine pitch 3D electrical interconnects has been proven by Vertical Circuits Inc. as a low cost, high reliability alternative to create System in Package (SIP) solutions.

This paper discusses the benefits of dispensing the 3D electrical interconnects instead of using traditional wire bond or high cost TSV processes to create the SIP. Pad pitches achieved are typically less than 65um between die pads, a conformal coating of a dielectric material with the subsequent selective laser ablation of the desired pads allows all lines to be dispensed in a single application with all lines adjacent to each other. Compared to traditional wire bond applications, the overall interconnect inductance is lower with comparable capacitive and resistive values enabling higher frequencies to be utilized.

Due to this process, complex multi-step stacking and bonding applications that jeopardize known good die (KGD) and increase the XY footprint of the SIP are eliminated. Furthermore, the entire die stacking process can be executed in a single step before the application of the electrical interconnect material; minimizing overall material handling and repetitive die stack processes that increase the probability of defects leading to expensive yield loss.

Methods for matching the Coefficient of Thermal Expansion (CTE) for the stacked components within a SIP will be demonstrated as well as surface treatments to enable fine pitch dispense and increase product reliability. JEDEC L3 reliability data will be presented to demonstrate SIP robustness using this technology.

Keywords: 3D Integration, Edge Interconnects, SIP, Printed Electronics

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