3D SUBSTRATE INNOVATION FOR VERY FINE PITCH FLIP-CHIP APPLICATIONSAuthors: Vern Solberg and Vage Oganesian
Company: STC-Madison and Tessera
Date Published: 10/11/2010 Conference: IWLPC (Wafer-Level Packaging)
There are a number of factors to consider when selecting an optimal semiconductor package configuration for the newer generations of high density controllers and processors; I/O requirement, package footprint, form factor, thermal dissipation, electrical performance, and cost. The more advanced microprocessor and ASIC semiconductors in wide use today have five to ten thousand bond sites and the I/O requirement for the high-end semiconductor is expected to increase by 30% in the very near future.
Although flip-chip assembly is widely accepted in the industry, the higher I/O and larger die outlines have increased assembly process challenges. A key concern is how to ensure consistent die-to-substrate interface, a critical barrier in achieving optimum assembly process yield. This paper describes a new interconnect solution that provides a very uniform array of raised solid copper contact features that are integrated onto the substrate interposer. The unique raised contact substrate enables semiconductor developers to significantly reduce contact pitch on the die without reducing pad size. Additionally, the flip-chip to substrate assembly process yield is proving to be significantly higher because the solder bumped die can be placed directly onto the raised contact features (eliminating the need for solder printing on the package substrate). Mounting the solder bumped die element on this uniform topography solves fundamental issues associated with underfill voiding and current package assembly process related defects.
Keywords: µPILR, flip-chip, substrate, interposer
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