IWLPC (Wafer-Level Packaging) Conference Proceedings


LAMINATE BASED FAN-OUT EMBEDDED DIE TECHNOLOGIES: THE OTHER OPTION

Authors: Theodore (Ted) G. Tessier, Mark Dhaenens, David Clark, Tanja Karila, Tuomas Waris
Company: FlipChip International, LLC and Imbera Electronics Inc.
Date Published: 10/11/2010   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Laminate based embedded die technologies have emerged as viable 2D and 3D packaging alternatives for higher integration density and low profile packaging. A key element of deploying such embedded die technologies is the willingness to change the semiconductor industry’s supply chain infrastructure to enable such revolutionary technology changes. Imbera and FlipChip International have been working collaboratively for more than 5 years to advance laminate based embedded die technologies by aligning the capabilities of wafer level fine pitch redistribution with build up printed wiring board substrate fabrication technologies. Successful technology applications to date have included a broad range of semiconductor packaging schemes including, Leadless leadframe package analogs, System in Package (SiP) and Fan-Out BGA and WLCSP array package solutions.

This paper provides an objective comparison of wafer level and laminate based embedded die fan-out technologies. Key 2D and 3D differentiators of laminate based approaches are presented. Technical and logistical considerations that enable these embedded die packages are discussed. Examples of recent embedded die semiconductor packages are described.

Keywords: Embeddable Die CustomizationTM, EDCTM, Redistribution, Laminate Embedded Die Fan-Out Packaging, iBGA®, iQFN®, iSiP®



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