EMBEDDED ACTIVE DEVICE PACKAGING TECHNOLOGY FOR REAL DDR2 MEMORY CHIPS
Authors: Yin-Po Hung, Tao-Chih Chang, Ching-Kuan Lee, Yuan-Chang Lee, Jing-Yao Chang, Chao-Kai Hsu, Shu-Man Li, Jui-Hsiung Huang, Fang-Jun Leu, Yu-Wei Huang, Ren-Shin Cheng and Tai-Hong Chen Company: Electronics and Optoelectronics Research Laboratories (EOL) and Industrial Technology Research Institute (ITRI) Date Published: 10/11/2010
IWLPC (Wafer-Level Packaging)
Abstract: As high-speed, high-density, and high-performance are the primary IC development targets, packaging becomes a key technology to bring out the best performance of the ICs. In this paper an embedded chip packaged module is developed for high speed memory devices. Embedding of semiconductor chips into organic substrates miniaturized the size of the package. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. In addition to wire bonding or w-BGA technologies, embedded package structure provides an alternative means to form redistribution circuits and electrical bonding pads. Meanwhile the electrical performance can be enhanced due to the wafer level package-like structure. Superior electrical performance is provided by forming shorter electrical path from chip pad to outer. In this study, a chip-in-substrate package (CiSP) using thin chips (~ 50um) of DDR2 memory with real function is disclosed by means of build-up technologies such as dielectric layer lamination, micro via drilling, and redistribution layer forming to implement the JEDEC-compliant DDR2 component. The PCB compatible process is a low-cost, high-yield, and versatile technology. Electrical performance similar to wafer level package and even better than wire bonding or w-BGA package can be achieved by adopting this proposed solution. A test vehicle of DDR2 memory with real function is studied to demonstrate the feasibility and electrical performance of this developed packaging. Relative process features will be presented to give a thorough construction of the package structure.