LOW COST, HIGH DENSITY CHIP-LAYER VIAS FOR CHIPS-FIRST STACKED PACKAGESAuthors: James E. Kohl, Ph.D., Charles W. Eichelberger, S. Keith Phillips, and Nancy G. Perkins
Company: EPIC Technologies Inc.
Date Published: 10/11/2010 Conference: IWLPC (Wafer-Level Packaging)
For system-in-a-package applications, chips-first packages are augmented by providing vias through the structural material in the chip-layer. Multiple interconnect layers are formed on each side of a chip-layer. Solder-bumps are formed on the bottom, and surface-mount pads on the top of each chip-layer. These layers can be stacked and interconnected by reflow of the solder.
A manufacturing method for fabricating the chip-layer vias has been developed and refined; it offers significant cost and density advantages over the other approaches: 1. laser drill and fill and 2. mold and fill. These other approaches use via filling processes from the printed circuit board industry along with special processes to deal with epoxy residues that might otherwise be left on the active IC surface.
In contrast, the method for fabricating chip-layer vias reported in this paper forms the vias by patterning a resist on a thin, seed metal layer on the alignment carrier. The resist thickness is somewhat thicker than the final thickness of the chips. Copper is plated up in the resist openings to form metal studs on the alignment carrier, which will become the chip-layer vias. After removal of the resist, chips are placed with their faces on to the alignment carrier, the structural material is added, and the surface is lapped flat. This Conductor-first photo-defined via process uses high yield wafer-level packaging processes to produce 100 micron vias on a 200 micron pitch, which meets the needs of the demanding target applications. In addition, high performance thermal conduits can be fabricated with the same process steps.
Keywords: chips-first, system-in-a-package, SiP, 3D-SiP, thermal management
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