IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Seung Wook Yoon, Meenakshi Prashant, Gaurav Sharma, Roger Emigh, Kai Liu, Sin Jae Lee, Ray Coronado, Yeong J. Lee, and Rajendra Pendse
Company: STATS ChipPAC
Date Published: 10/11/2010   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Demand for WLP (Wafer Level Package) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. WLP is the upcoming future packaging technology. The increasing demand for new and more advanced electronic products with smaller form factor and superior functionality and performance, is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology.

This paper will highlight some of the recent characterization works of electrical, thermal and mechanical performance of eWLB packaging. The performance compared with other packaging format, ie. FI-WLP (Fan In-WLP) and fcBGA (flipchip Ball Grid Array) packages is discussed. Thermal resistance, ?ja of eWLB packaging is studied and it is found comparable with those of FI-WLP and fcBGA. Thermal characterization activity is carried out to investigate the effect on eWLB configuration with power loading. Thin film based integrated passives on the fan-out area (mold material) of the eWLB is also analyzed during RF performance characterization. Due to the low-loss property of the mold material, plated Cu inductors showed high quality-factor (Q) performance. The mold material in fan-out area is not only used as a supporting substrate, but also serves as the package substrate, which allows the high-Q inductors to be implemented with other RF chips in one single package. Parasitic electrical performance and characterization works will be presented in this paper. eWLB package warpage behavior with temperature profile observed with Thermo-Moire method result will be presented in this paper too.

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