IWLPC (Wafer-Level Packaging) Conference Proceedings


ENABLING COMPREHENSIVE AND EFFICIENT TEST OF 3D CHIPS BY STANDARDIZING THE TEST ACCESS ARCHITECTURE

Author: Al Crouch
Company: ASSET InterTech, Inc.
Date Published: 10/11/2010   Conference: IWLPC (Wafer-Level Packaging)


Abstract: There are several technical difficulties associated with 3D, but one large problem that is a carryover from both MCMs and SoCs is the test problem. Today’s modern ICs include many IP cores and functional units and each one may come with a wealth of embedded features for test and debug, such as manufacturing scan logic, logic and memory BIST, and embedded temperature/voltage monitors. Developing an architecture that allows access, configuration and operation of these embedded test features on 2D chips is always problematic, but combining multiple 2D die into a 3D diestack with package pins on only one die in the stack compounds the validation, test and debug issues exponentially. This paper will discuss the problems with 3D test and outline some of the proposals that an IEEE 3D study group has been investigating as the basis for a working group for an IEEE standard.

Key words: 3D chips, chip test, TSV, through-silicon vias



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