IWLPC (Wafer-Level Packaging) Conference Proceedings


Authors: Thorsten Meyer, Gerald Ofner, Christian Geissler and Klaus Pressel
Company: Infineon Technologies
Date Published: 10/11/2010   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The challenges of today's device packaging are manifold. The driving factors for package development are packaging and test cost, miniaturization with rising number of I/Os per area, continuously increasing operating frequencies and data rates, thermal requirements, the integration of additional functionality and the package reliability.

Fan-Out Wafer Level Packaging is one of the upcoming future packaging technologies, which provides a solution for those challenges. Like for standard wafer level packaging technologies the lead frame or interposer and the first level interconnect (chip to package) of classical packages melt into a thin-film redistribution layer. This provides electrical and thermal performance advantages, allows miniaturization and is a low cost packaging and test solution due to the high parallelism in processing.

The fan-out embedded Wafer Level Ball Grid Array (eWLB) is not restricted in the applicable number of I/Os on the package and provides excellent potential for including additional functionality and reliability.

The increasing demand for new and more advanced electronic products with superior functionality and performance is driving the integration of functionality for future packaging technologies. The major approach for system integration is a side-by-side Multi-Chip. We introduce Infineon’s Multi-Chip embedded Wafer Wafer Level Ball Grid Array (Multi-Chip eWLB).

Key words: eWLB, Fan-out WLB, Wafer Level Package, SiP, System in Package, Side by side

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