WAFER LEVEL EMBEDDED SYSTEM IN PACKAGE (WL-ESiP) FOR 3D SiP SOLUTIONAuthors: In-Soo Kang, Gi-Jo Jung, Byoung-Yool Jeon, Jae-Hyouk Yoo and Byeung-Gee Kim
Company: Nepes Corporation
Date Published: 10/11/2010 Conference: IWLPC (Wafer-Level Packaging)
Then, a normal size WL-eSiP was designed in daisy chain pattern and fabricated to evaluate the package level and board level reliabilities for verifying process and package reliability. The mother chip size is 4mm x4mm and daughter chip size 2.95mm x 2.31mm. Firstly, whole manufacturing process of WL-eSiP was developed. Then, package level reliability tests were performed for MSL1, PCT (121/ 100%RH/ 2atm), TC (-40/125) and HTS (150) and all items have been passed. For board level reliability test, TC (-40/125) and drop (1500G/ 0.5ms) tests were passed.
Secondly, for broader applications, stress improvement on each process step for larger size WL-eSiP was done through warpage and curvature evaluation. The feasibility test for the process of WL-eSiP with the mother chip of 6mm x 6mm size was done. Then, the fabricated WL-eSiP will be evaluated for package level reliability tests of MSL3, PCT (121/ 100%RH/ 2atm), TC (-40/125) and HTS (150).
Thirdly, for module application of mobile products embedding multi daughter dies into one mother die and IPD (Integrated Passive Device) application were suggested and developed. IPD was considered to be integrated onto mother die or molding side and two small daughter dies to be mounted onto mother die.
Key words: WL-eSiP, wafer level molding, 3D SiP, Mobile
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