Authors: Po-Yi Chang and Yi-Sha Ku Company: Industrial Technology Research Institute Date Published: 10/11/2010
IWLPC (Wafer-Level Packaging)
Abstract: A self-designed measuring system base on the fringe reflection method has been demonstrated for the wafer topography measurement. The phase shifting technique is employed to enhance the measurement resolution and the phase unwrapping algorithm is used to reconstruct the full 3D topography. A bare silicon wafer is selected as a reference mirror in our system. The warpage measurement results of a 4-inch Au coated wafer were verified by the probe-type surface analyzer KOSAKA ET-4000A. The discrepancy is within 2µm. Another 8-inch silicon wafer with TSV array patterns is measured with warpage of 122µm.