Authors: Martin Wilke, Kai Zoschke, Julia Röder, Veronika Glaw, Michael Töpper, Ingrid Kuna, Karin Samulewicz, Oswin Ehrmann, Klaus-Dieter Lang and Herbert Reichl Company: Fraunhofer IZM Date Published: 10/11/2010
IWLPC (Wafer-Level Packaging)
Abstract: The ongoing efforts of increasing the resolution of CMOS imagers for consumer products led to an effective miniaturization in pixel sizes of down to 1.8 µm. This technological progress enables besides high pixel count cameras also the production of high quality imagers which can have a size of smaller than 1 x 1mm2 assuming a CIF (Common Intermediate Format) resolution. The small size of these imager chips opens new applications in the medical (endoscopes) and automotive (human machine interfaces, driver monitoring) sector as long as the packaging is able to assemble the optics and imager while keeping the form factor of the package small. It is therefore technically and ecologically reasonable to realise such micro cameras on wafer level using through silicon vias. This paper presents the packaging process chain starting from the imager wafer to the singulated micro camera device package. All process steps are carried out on wafer level including the optics assembly. The size of the imager bond pads is 65µm, which are contacted by tapered TSVs. The polymer based redistribution layers (RDL) are realised by spray coating. The paper discusses furthermore the potential to form a spin coated RDL taking the silicon thickness and via size into account.