IWLPC (Wafer-Level Packaging) Conference Proceedings


MINIATURIZED WLP FOR MEMS

Authors: Risto Mutikainen, Ph.D., Sami Nurmi, Ph.D., Tapani Alander, Ph.D., Esko Sirén, Lic. Tech. and Heikki Kuisma, M.Sc.
Company: VTI Technologies
Date Published: 10/11/2010   Conference: IWLPC (Wafer-Level Packaging)


Abstract: MEMS packaging poses specific issues especially of mechanical origin. Being a mechanical device, the thermal strains from packaging technology selected are not allowed to sacrifice the device performance. The reliability at assembly and over life must also be designed in. Environmental stresses may neither interact with the device output. Packaging caused effects must be complied with careful design optimization involving whole measurement system with specific requirements on each case. Depending on the MEMS and measuring/interfacing electronics requirements, real estates needed for each part can set more limits especially for consumer electronics market to overcome, which can be addressed by suitable technology choices, packaging concept selection and by proper design. For more, good manufacturability at packaging modules may set several additional requirements for MEMS processes selected. Key results from MEMS WLP packaging platform suitable for several inertial or other quantities are presented addressing the above issues. The effects of packaging caused phenomena are discussed. When being able to utilize standard packaging processes, competitive cost structure can be achieved. As a result, applying WLP on MEMS offers unique advantages on miniaturization and for functionality combination.

Key words: MEMS packaging, WLP, Flip chip



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