DEMONSTRATION OF ULTRA-THIN SI GRINDING PROCESS CONTROLLED BY IN-SITU NON-CONTACT GAUGE FOR 3D STACKED IC (3D-SIC)
Authors: Ming Zhao, Greet Verbinnen, Anne Jourdain, Eric Beyne, Bart Swinnen, Leonardus Leunissen, Tomotaka Tabuchi, Shinji Yoshida, and Susumu Hayakawa Company: IMEC VZW, DISCO Corporation, DISCO HI-TECH EUROPE GmbH Date Published: 10/11/2010
IWLPC (Wafer-Level Packaging)
Abstract: In order to enable 3D-SIC technology, the device wafer needs to be aggressively thinned down to less than ~100 µm usually on a carrier by e.g. grinding process. One of the key requirements for such a wafer thinning process is to precisely control the device wafer final thickness with minimum total thickness variation. In conventional grinding process using contact mechanical height gauges, the device wafer thickness is indirectly controlled by gauging the total thickness of the bonded wafer stack (device wafer bonded on the carrier wafer), which requires a tighter thickness specification for the carrier wafer and bonding glue, as well as complicated and time-consuming process steps. Therefore, it highly demands an in-line metrology for such an in-situ grinding process control. In this work, we have demonstrated a grinding process by in-situ monitoring directly on the device wafer thickness out of the bonded stack. The process was performed on a Disco DGP8761 grinder polisher equipped with optical non-contact gauges, which measure the device wafer thickness using interference spectrometry based on the reflected light signals from the top and bottom surface of the device wafer. A large variety of test wafers, including 200 mm and 300 mm device wafers (either blanket or containing Cu filled TSVs) bonded either on grinding tapes or Si carriers, have been successfully ground using such a process to a final thickness ranging from 160 µm to 15 µm. Post grinding measurement using optical interferometry and crosssectional scanning electron microscope showed the final mean device wafer thickness was precisely controlled in a range of ± ~3 µm around the target final thickness, with wafer-to-wafer non-uniformity <~1 µm in a batch.