A COST-EFFECTIVE PROCESS FOR EDGE PROTECTION OF WAFERS
Authors: Ramachandran K. Trichur, Gary J. Brand, Curtis Planje, Xie Shao Company: Brewer Science, Inc. Date Published: 10/24/2010
Abstract: With the great demand for smaller, faster, highly functional devices, vertical integration of integrated circuits (ICs) is essential to reduce “real estate” and improve performance. Through-silicon vias (TSVs) are an integral element for the realization of three-dimensional (3-D) interconnects for vertical integration in these advanced ICs. Currently, deep reactive ion etching (DRIE), laser drilling, or wet etching technologies are used for fabricating TSVs. DRIE is the predominant choice for high-density TSV applications, while wet etching of silicon is an economical alternative for low-density TSV applications due to batch processing capabilities and low cost of ownership. Typically silicon nitride or silicon dioxide films are used as a mask during wet chemical etching. Here we use a spin-coatable polymer etch mask as an alternate masking material during wet etching of silicon. During such etching, the edge of the wafer gets attacked by the etch chemical regardless of the mask material used due to pinholes, partial coverage of the edge, etc. The edge attack results in a knife-like edge along the wafer edge and presents many issues, especially wafer breakage during thin-wafer handling and packaging. In this paper we present an edge protection method to prevent damage to the edge of the wafer during wet etching of silicon to create TSVs. Here we use a specially modified coating tool to deposit the spin-coatable etch mask onto the wafer and its edges in a seamless coating, thus protecting the wafer edge from any damage during silicon etching.