QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY
Authors: Jinda Songninluck, Theeraphong Kanjanupathum, and Teng Hoon Ng Company: Celestica, Technology Development-Thailand Date Published: 10/24/2010
Abstract: Acceptable levels of voiding in solder joints have been and continue to be a topic for research. The continuing evolution and miniaturization electronic packages and the associated problems with thermal integrity and heat evolution require that packages be evaluated for applications in high complexity applications such as enterprise computing and telecommunications. These applications utilize large thick printed wiring board(PWB) and include high thermal mass parts which necessitate extended thermal profiles. Smaller packages will be exposed to long soak zones and high peak temperatures. Additionally, the mixture of technology requires that these smaller packages be assembled using process parameters and materials that are not associated with the consumer applications where they were originally common. Thermal fatigue characteristics for these packages will also be affected by the change in assembly characteristics, specifically the increased stiffness generated by thick high layer count PWBs.
In this study, a series of process parameters and stencil designs are being evaluated through a range of thermal profiles to establish optimized paste volumes and void percentages. And the reliability of the resulting assemblies are then being evaluated by accelerated thermal cycling (ATC). Process and test methods, solder joint microstructure metallurgy, test results and failure analysis are being discussed.