ICSR (Soldering and Reliability) Conference Proceedings


Effect Of Assembly Variations On Triple Stack Package On Package Yield And Reliability

Authors: Jimmy Chow, Heather McCormick, Russell Brush, Joel Trudell and Roden Cortero
Company: Celestica Inc.
Date Published: 5/17/2010   Conference: ICSR (Soldering and Reliability)


Abstract: As OEMs are constantly under tremendous pressure to reduce product size and increase functionality, finding component real estate to accommodate new features on circuit board designs is an increasingly difficult task. 3D packaging is an attractive solution to mitigate issues of decreasing board real estate. By stacking logic and memory devices over a single PCB land pattern, the designer is able to achieve dramatic increases in density, and can also realize performance improvements through shorter connections between the memory and logic devices. Triple Stack Package on Package devices (PoP) are a new variation of the PoP concept which stacks three devices over a single board footprint, while conventional PoP components stack only two devices.

This paper is focused on the manufacturability and reliability issues of a 12mm square Triple Stack PoP component. The pitch of the bottom device, soldered to the board, is 0.5mm allowing for 305 I/O while the pitch of both the middle and upper package is 0.65mm, permitting 128 I/O on each device layer. This study compares assembly yields for both dip flux and dip paste PoP assembly processes, including the effect of variations in dip depth. The reliability of the different assembly variations in accelerated thermal cycling (ATC) is presented, including underfilled and non-underfilled variations. Failure analysis results are presented to help better understand the failure modes for this package.

Key words: Triple Stack Package on Package (PoP), 3-D Packaging, Dip Flux, Dip Paste, Reliability



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