IMPORTANT CONSIDERATIONS IN PACKAGING A SMALL HALL-EFFECT SENSORAuthors: Ron Molnar and Jeff Wise
Company: AZ Tech Direct, LLC
Date Published: 1/26/2010 Conference: Pan Pacific Symposium
The search for an appropriate package and assembly facility, the issues encountered during assembly of qualification lots, the assembly process control data, and the chip/package reliability test results are described in detail. The individual constraints on the packaging, in and of themselves, are achievable with today’s technologies, however in combination they limited the choice of packages, direct materials, and suppliers. The trade-offs made, the merits and disadvantages of each approach, and the ultimate decisions and results are described. Details of the final package construction, die preparation issues, the assembly qualification build, and environmental reliability test results are revealed. A total cost analysis of wafer fab and sort, die prep, assembly and final test, and packing is presented.
Initial work in developing this new Hall-effect sensor showed that the die size could be shrunk significantly, thereby reducing the current path width to as little as 0.5 µm without sacrificing performance. Thus, the size of the future sensor chip designs will be limited only by the minimum contact (wire bond or flip chip) pad sizes and their minimum pitch dictated by assembly design rules. The drive for ever smaller Hall-effect sensors will push the limits of conventional small-scale package manufacturing and may result in wafer-level packages if the cost targets can be met. Ongoing research and development is focused on low-cost, flip chip implementations in which the cost of die rework vs. the cost of sub-assembly scrap will be considered.
Key words: Hall-effect, GaAs, SC70, package, assembly
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