FROM THE SINGLE CHIP TO THE WAFER INTEGRATIONAuthors: Gilles Poupon, Jean Charles Souriau, Hervé Boutry, Jean Brun, and Nicolas Sillon
Company: CEA-LETI Minatec
Date Published: 1/26/2010 Conference: Pan Pacific Symposium
Companies that desire an "in-house solution" will prefer WLP because one of the benefits of the wafer level packaging is a simplified supply and value chain. Furthermore, for small companies (not IDM’s), one of main consideration is to use generic technologies which can be applied on chips coming from different sources because they have no direct access to wafer manufacturing. To be compatible for chip multi-sourcing one of the most know examples on wafer level packaging is the fan-out wafer level structure This concept, proposed by major companies (Infineon, Freescale, ...), consists of rebuilding a wafer from heterogeneous Known Good Die (ASIC, sensor, memory, optic component etc.).
After having established the current state of the art, the objective of this paper is to identify the various technological concepts and to give a focus on Chip in Wafer in Silicon technology developed at CEA-LETI.
Key words: wafer level packaging, embedded components, rebuilt wafer, 3D integration
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