Pan Pacific Symposium Conference Proceedings


Authors: M. Juergen Wolf, et al.
Company: Fraunhofer Institute for Reliability and Microintegration IZM
Date Published: 1/26/2010   Conference: Pan Pacific Symposium

Abstract: Heterogeneous integration is one of the key topics for future system integration to address today’s requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex system integration. “More than Moore” will be required due to tighter integration of system level components at the package level. This trend leads to advanced 3D System in Package solutions (SiP).

One of the most promising technology approaches is 3D packaging which involves a set of different integration ap-proaches. Silicon interposer with TSV´s offers a new possi-bility to merge advanced devices e.g. high pin count ASICs, memories and MEMS using a silicon interposer with Through Silicon Vias (TSVs). Two applications using a Si Interposer are described in this paper.

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