TOMBSTONE CAPACITORS REVISITED, NOW DO WE NEED A PSL (PLATING SENSITIVITY LEVEL) SPECIFICATION FOR CHIP COMPONENTS
Authors: John Maxwell and Chris England Company: Johanson Dielectrics, Inc. Date Published: 10/4/2009
Abstract: Drawbridges or tombstone assembly defects for chip components has not been a topic of discussion for some years but these defects are on the increase as low cost vendors are providing parts into the electronic component supply chain. Land pattern design standards, improved solder paste materials and improved reflow soldering systems have all but banished tombstone type of defects from electronic assembly. Unfortunately it has raised its ugly head with a new source of these old defects surfacing during ongoing competitor component evaluation of low cost Asian manufacturers of MLC capacitors. Sudden out gassing or venting of trapped nickel plating solutions has been observed in a number of BME (Base Metal Electrode) capacitors resulting in a new source of drawbridge or tombstone solder joint defects in chips as small as 0402 and as large as 1825. Perhaps it is now time to add a test technique to evaluate plating sensitivity levels (PSL) when these chip components are reflow soldered like MSL1,2 (Moisture Sensitivity Levels) ratings for molded components to minimize popcorn damage due to steam formation within the package. Unfortunately or fortunately depending on ones point of view there can only be a pass fail system vs. different levels found in MSL ratings for molded IC packages.